vue-files-preview-inno/es/node_modules/highlight.js/lib/languages/vhdl.mjs.map

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{"version":3,"file":"vhdl.mjs","sources":["../../../../../../node_modules/highlight.js/lib/languages/vhdl.js"],"sourcesContent":["/*\nLanguage: VHDL\nAuthor: Igor Kalnitsky <igor@kalnitsky.org>\nContributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>\nDescription: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.\nWebsite: https://en.wikipedia.org/wiki/VHDL\nCategory: hardware\n*/\n\nfunction vhdl(hljs) {\n  // Regular expression for VHDL numeric literals.\n\n  // Decimal literal:\n  const INTEGER_RE = '\\\\d(_|\\\\d)*';\n  const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n  const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';\n  // Based literal:\n  const BASED_INTEGER_RE = '\\\\w+';\n  const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n\n  const NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n\n  const KEYWORDS = [\n    \"abs\",\n    \"access\",\n    \"after\",\n    \"alias\",\n    \"all\",\n    \"and\",\n    \"architecture\",\n    \"array\",\n    \"assert\",\n    \"assume\",\n    \"assume_guarantee\",\n    \"attribute\",\n    \"begin\",\n    \"block\",\n    \"body\",\n    \"buffer\",\n    \"bus\",\n    \"case\",\n    \"component\",\n    \"configuration\",\n    \"constant\",\n    \"context\",\n    \"cover\",\n    \"disconnect\",\n    \"downto\",\n    \"default\",\n    \"else\",\n    \"elsif\",\n    \"end\",\n    \"entity\",\n    \"exit\",\n    \"fairness\",\n    \"file\",\n    \"for\",\n    \"force\",\n    \"function\",\n    \"generate\",\n    \"generic\",\n    \"group\",\n    \"guarded\",\n    \"if\",\n    \"impure\",\n    \"in\",\n    \"inertial\",\n    \"inout\",\n    \"is\",\n    \"label\",\n    \"library\",\n    \"linkage\",\n    \"literal\",\n    \"loop\",\n    \"map\",\n    \"mod\",\n    \"nand\",\n    \"new\",\n    \"next\",\n    \"nor\",\n    \"not\",\n    \"null\",\n    \"of\",\n    \"on\",\n    \"open\",\n    \"or\",\n    \"others\",\n    \"out\",\n    \"package\",\n    \"parameter\",\n    \"port\",\n  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\"bit_vector\",\n    \"file_open_kind\",\n    \"file_open_status\",\n    \"std_logic\",\n    \"std_logic_vector\",\n    \"unsigned\",\n    \"signed\",\n    \"boolean_vector\",\n    \"integer_vector\",\n    \"std_ulogic\",\n    \"std_ulogic_vector\",\n    \"unresolved_unsigned\",\n    \"u_unsigned\",\n    \"unresolved_signed\",\n    \"u_signed\",\n    \"real_vector\",\n    \"time_vector\"\n  ];\n  const LITERALS = [\n    // severity_level\n    \"false\",\n    \"true\",\n    \"note\",\n    \"warning\",\n    \"error\",\n    \"failure\",\n    // textio\n    \"line\",\n    \"text\",\n    \"side\",\n    \"width\"\n  ];\n\n  return {\n    name: 'VHDL',\n    case_insensitive: true,\n    keywords: {\n      keyword: KEYWORDS,\n      built_in: BUILT_INS,\n      literal: LITERALS\n    },\n    illegal: /\\{/,\n    contains: [\n      hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.\n      hljs.COMMENT('--', '$'),\n      hljs.QUOTE_STRING_MODE,\n      {\n        className: 'number',\n        begin: NUMBER_RE,\n        relevance: 0\n      },\n      {\n        className: 'string',\n        begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n        contains: [ hljs.BACKSLASH_ESCAPE ]\n      },\n      {\n        className: 'symbol',\n        begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n        contains: [ hljs.BACKSLASH_ESCAPE ]\n      }\n    ]\n  };\n}\n\nmodule.exports = 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