teroshdl/test/templates/examples/vhdl/component_mix.txt

Backend for terosHDL IDE

component arith_counter_gray
  generic (
    BITS : positive;
    INIT : natural
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    inc : in std_logic;
    dec : in std_logic;
    val : out std_logic_vector(BITS-1 downto 0);
    cry : out std_logic
  );
end component;