teroshdl/test/templates/examples/verilog/signals.txt

Backend for terosHDL IDE

  reg r_reset;
  reg r_txclk;
  reg r_ld_tx_data;
  reg [7:0] r_tx_data;
  reg r_tx_enable;
  reg r_tx_out;
  reg r_tx_empty;
  reg r_rxclk;
  reg r_uld_rx_data;
  reg [7:0] r_rx_data;
  reg r_rx_enable;
  reg r_rx_in;
  reg r_rx_empty;