teroshdl/test/examples/verilog_error/example_3.json

Backend for terosHDL IDE

{
  "ICARUS":
  [
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [10,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [13,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [15,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [18,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [19,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [20,0]
      },
      "description": "Invalid variable list in port declaration."
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [22,0]
      },
      "description": "Invalid module instantiation"
    },
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [23,0]
      },
      "description": "Invalid module instantiation"
    }
  ],
  "VERILATOR":
  [
    { "severity": "error",
      "location": {
        "file": "example_3.v",
        "position": [23,0]
      },
      "description": "Unsupported: Blocked and non-blocking assignments to same variable: uart_rx.state"
    }
  ]
}