teroshdl/test/examples/verilog/example_10.json

Backend for terosHDL IDE

{
  "libraries": [],
  "entity": {
    "name": "add2_and_clip_reg",
    "description": "\n  \n\n  \n\n  \n\n\n\n \n  \n\n \n  And more core description can be added here\n \n"
  },
  "generics": [
    {
      "name": "WIDTH",
      "type": "",
      "default_value": "16",
      "description": " pepe\r"
    }
  ],
  "ports": [
    {
      "name": "clk",
      "direction": "input",
      "type": "",
      "default_value": "",
      "description": "",
      "start_line": 24,
      "group": ""
    },
    {
      "name": "rst",
      "direction": "input",
      "type": "",
      "default_value": "",
      "description": "",
      "start_line": 25,
      "group": ""
    },
    {
      "name": "in1",
      "direction": "input",
      "type": "[WIDTH-1:0]",
      "default_value": "",
      "description": "**descrition**",
      "start_line": 26,
      "group": ""
    },
    {
      "name": "in2",
      "direction": "input",
      "type": "[WIDTH-1:0]",
      "default_value": "",
      "description": "",
      "start_line": 27,
      "group": ""
    },
    {
      "name": "strobe_in",
      "direction": "input",
      "type": "",
      "default_value": "",
      "description": "",
      "start_line": 28,
      "group": ""
    },
    {
      "name": "sum",
      "direction": "output",
      "type": "[WIDTH-1:0]",
      "default_value": "",
      "description": "",
      "start_line": 29,
      "group": ""
    },
    {
      "name": "strobe_out",
      "direction": "output",
      "type": "",
      "default_value": "",
      "description": "",
      "start_line": 30,
      "group": ""
    }
  ],
  "body": {
    "processes": [
      {
        "name": "unnamed",
        "sens_list": "@(posedge clk)",
        "description": "",
        "start_line": 36
      },
      {
        "name": "unnamed",
        "sens_list": "@(posedge clk)",
        "description": "",
        "start_line": 42
      }
    ],
    "instantiations": [
      {
        "name": "add2_and_clip",
        "type": "add2_and_clip",
        "description": "",
        "start_line": 34
      }
    ]
  },
  "declarations": {
    "types": [],
    "signals": [
      {
        "name": "sum_int",
        "type": "wire [WIDTH-1:0]",
        "description": "",
        "start_line": 32
      }
    ],
    "constants": [],
    "functions": []
  },
  "info": {
    "file": "example_8.vhd",
    "date": "2020-07-10",
    "copyright": " Copyright (c) 2021 by TerosHDL\n               GNU Public License\n   This program is free software: you can redistribute it and/or modify\n   it under the terms of the GNU General Public License as published by\n   the Free Software Foundation, either version 3 of the License, or\n   (at your option) any later version.\n   This program is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n   GNU General Public License for more details.\n   You should have received a copy of the GNU General Public License\n   along with this program.  If not, see <https://www.gnu.org/licenses/>",
    "author": "el3ctrician (elbadriahmad@gmail.com)",
    "version": "0.1",
    "brief": "Some description can be added here \n  also in multi-lines",
    "details": "Another description can be added here"
}
}