edacation/dist/project/iverilog.js

Library and CLI for interacting with Yosys and nextpnr.

"use strict";
var __importDefault = (this && this.__importDefault) || function (mod) {
    return (mod && mod.__esModule) ? mod : { "default": mod };
};
Object.defineProperty(exports, "__esModule", { value: true });
exports.getIVerilogWorkerOptions = exports.getIVerilogOptions = exports.parseIVerilogArguments = void 0;
const path_1 = __importDefault(require("path"));
const string_args_parser_1 = require("string-args-parser");
const util_js_1 = require("../util.js");
const target_js_1 = require("./target.js");
const DEFAULT_OPTIONS = {
    testbenchFile: undefined
};
const parseIVerilogArguments = (args) => args.flatMap((arg) => (0, string_args_parser_1.parseArgs)(arg));
exports.parseIVerilogArguments = parseIVerilogArguments;
const getIVerilogOptions = (configuration, targetId) => (0, target_js_1.getOptions)(configuration, targetId, 'iverilog', DEFAULT_OPTIONS);
exports.getIVerilogOptions = getIVerilogOptions;
const getIVerilogWorkerOptions = (project, targetId) => {
    const configuration = project.getConfiguration();
    const target = (0, target_js_1.getTarget)(configuration, targetId);
    const options = (0, exports.getIVerilogOptions)(configuration, targetId);
    // Input files
    const designFiles = project.getInputFiles().filter((inputFile) => inputFile.type === 'design' && util_js_1.FILE_EXTENSIONS_VERILOG.includes(path_1.default.extname(inputFile.path).substring(1))).map(file => file.path);
    let testbenchFile = options.testbenchFile;
    if (!testbenchFile) {
        // Auto-select from testbench input files
        const allTestbenches = project.getInputFiles().filter((file) => file.type === 'testbench');
        if (allTestbenches.length === 0)
            throw new Error('Could not auto-select testbench file: no input files marked as such');
        testbenchFile = allTestbenches[0].path;
    }
    const generatedInputFiles = designFiles.concat([testbenchFile]);
    const inputFiles = (0, target_js_1.getCombined)(configuration, targetId, 'iverilog', 'inputFiles', generatedInputFiles).filter((f) => !!f);
    // Output files
    const compiledFile = (0, target_js_1.getTargetFile)(target, 'simulator.vvp');
    const generatedOutputFiles = [compiledFile, `${path_1.default.parse(testbenchFile).name}.vcd`];
    const outputFiles = (0, target_js_1.getCombined)(configuration, targetId, 'iverilog', 'outputFiles', generatedOutputFiles).filter((f) => !!f);
    // Args
    const generatedCompileArgs = [
        '-o', compiledFile,
        ...designFiles,
        testbenchFile,
    ];
    const compileArgs = (0, target_js_1.getCombined)(configuration, targetId, 'iverilog', 'arguments', generatedCompileArgs, exports.parseIVerilogArguments);
    return {
        inputFiles,
        outputFiles,
        target,
        options,
        steps: [
            {
                id: 'iverilog',
                tool: 'iverilog',
                arguments: compileArgs
            },
            {
                id: 'vvp',
                tool: 'vvp',
                arguments: [compiledFile]
            }
        ]
    };
};
exports.getIVerilogWorkerOptions = getIVerilogWorkerOptions;
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