edacation
Version:
Library and CLI for interacting with Yosys and nextpnr.
73 lines • 3.83 kB
JavaScript
;
var __importDefault = (this && this.__importDefault) || function (mod) {
return (mod && mod.__esModule) ? mod : { "default": mod };
};
Object.defineProperty(exports, "__esModule", { value: true });
exports.getIVerilogWorkerOptions = exports.parseIVerilogArguments = exports.generateIVerilogWorkerOptions = exports.getIVerilogOptions = exports.getIVerilogDefaultOptions = void 0;
const path_1 = __importDefault(require("path"));
const string_args_parser_1 = require("string-args-parser");
const util_js_1 = require("../util.js");
const target_js_1 = require("./target.js");
const DEFAULT_OPTIONS = {
testbenchFile: undefined
};
const getIVerilogDefaultOptions = (configuration) => (0, target_js_1.getDefaultOptions)(configuration, 'iverilog', DEFAULT_OPTIONS);
exports.getIVerilogDefaultOptions = getIVerilogDefaultOptions;
const getIVerilogOptions = (configuration, targetId) => (0, target_js_1.getOptions)(configuration, targetId, 'iverilog', DEFAULT_OPTIONS);
exports.getIVerilogOptions = getIVerilogOptions;
const generateIVerilogWorkerOptions = (configuration, projectInputFiles, targetId) => {
const target = (0, target_js_1.getTarget)(configuration, targetId);
const options = (0, exports.getIVerilogOptions)(configuration, targetId);
const files = projectInputFiles.filter((inputFile) => inputFile.type === 'design' && util_js_1.FILE_EXTENSIONS_VERILOG.includes(path_1.default.extname(inputFile.path).substring(1)));
const designFiles = files.map((file) => file.path);
let testbenchFile = options.testbenchFile;
if (!testbenchFile) {
// Auto-select from testbench input files
const allTestbenches = projectInputFiles.filter((file) => file.type === 'testbench');
if (allTestbenches.length === 0)
throw new Error('Could not auto-select testbench file: no input files marked as such');
testbenchFile = allTestbenches[0].path;
}
const inputFiles = designFiles.concat([testbenchFile]);
const compiledFile = (0, target_js_1.getTargetFile)(target, 'simulator.vvp');
const outputFiles = [compiledFile, `${path_1.default.parse(testbenchFile).name}.vcd`];
const compileArgs = [];
compileArgs.push('-o', compiledFile);
compileArgs.push(...designFiles);
compileArgs.push(testbenchFile);
const steps = [
{ tool: 'iverilog', arguments: compileArgs },
{ tool: 'vvp', arguments: [compiledFile] }
];
return {
inputFiles,
outputFiles,
target,
options,
steps
};
};
exports.generateIVerilogWorkerOptions = generateIVerilogWorkerOptions;
const parseIVerilogArguments = (args) => args.flatMap((arg) => (0, string_args_parser_1.parseArgs)(arg));
exports.parseIVerilogArguments = parseIVerilogArguments;
const getIVerilogWorkerOptions = (project, targetId) => {
const generated = (0, exports.generateIVerilogWorkerOptions)(project.getConfiguration(), project.getInputFiles(), targetId);
const inputFiles = (0, target_js_1.getCombined)(project.getConfiguration(), targetId, 'iverilog', 'inputFiles', generated.inputFiles).filter((f) => !!f);
const outputFiles = (0, target_js_1.getCombined)(project.getConfiguration(), targetId, 'iverilog', 'outputFiles', generated.outputFiles).filter((f) => !!f);
const target = generated.target;
const options = generated.options;
const steps = generated.steps.map((step) => {
const tool = step.tool;
const args = (0, target_js_1.getCombined)(project.getConfiguration(), targetId, 'iverilog', 'commands', step.arguments);
return { tool, arguments: args };
});
return {
inputFiles,
outputFiles,
target,
options,
steps
};
};
exports.getIVerilogWorkerOptions = getIVerilogWorkerOptions;
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