cirsim/src/help/memory16.html

Cirsim Circuit Simulator

<p>The Memory component implements a simple 16-bit Memory Bank.
  Memory is an array of bytes. The A (address) input selects a memory location that is output on the R
  output. The component implements 16-bit memory,
  so all accesses are considered to be multiples of two and retrieve two bytes. Memory is retrieved in little-endian
  mode (first byte is the least significant byte).</p>
<p>A clock cycle on the clock input writes the memory component with the value on the W (write) input. The value on
W is written to memory on the rising clock edge.</p>
<p>Memory can be specified in the component dialog box as a sequence of Hexadecimal byte values:</p>
<pre>12 34 a8 93 b7 00 12 9a</pre>
<p>Spaces and new-lines are ignored. Addresses can optionally be included at the beginning of lines:</p>
<pre>0000: 12 34 a8 93 b7 00 12 9a
0008: 18 b7</pre>
<figure><img src="img/memory16.png" width="241" height="221" alt="Memory 16 Component"></figure>
<p>The clock input will always write memory when cycles to true and back to false. The memory component
does not have a <em>write enable</em> input. However, it is easy to make one by using an AND gate:</p>
<figure><img src="img/memory16we.png" width="277" height="256" alt="Add a Write Enable to the Memory 16 component"></figure>