cirsim/dist/cirsim/help/and3.html

Cirsim Circuit Simulator

<p>The output of a three-input AND gate is <em>true</em> if all inputs are true.</p>
<figure><img src="img/and3.png" width="264" height="137" alt="3-input AND Gate"></figure>
<h3>Truth Table</h3>
<table class="truth-table">
  <tr><th>A</th><th>B</th><th>C</th><th>O</th></tr>
  <tr><td>0</td><td>0</td><td>0</td><td>0</td></tr>
  <tr><td>0</td><td>0</td><td>1</td><td>0</td></tr>
  <tr><td>0</td><td>1</td><td>0</td><td>0</td></tr>
  <tr><td>0</td><td>1</td><td>1</td><td>0</td></tr>
  <tr><td>1</td><td>0</td><td>0</td><td>0</td></tr>
  <tr><td>1</td><td>0</td><td>1</td><td>0</td></tr>
  <tr><td>1</td><td>1</td><td>0</td><td>0</td></tr>
  <tr><td>1</td><td>1</td><td>1</td><td>1</td></tr>
</table>