@uiw/file-icons/lib/Verilog.js

File icons in the file tree

"use strict";

var _interopRequireDefault = require("@babel/runtime/helpers/interopRequireDefault")["default"];
Object.defineProperty(exports, "__esModule", {
  value: true
});
exports.Verilog = void 0;
var _objectSpread2 = _interopRequireDefault(require("@babel/runtime/helpers/objectSpread2"));
var _react = _interopRequireDefault(require("react"));
var _jsxRuntime = require("react/jsx-runtime");
var Verilog = function Verilog(props) {
  return /*#__PURE__*/(0, _jsxRuntime.jsx)("svg", (0, _objectSpread2["default"])((0, _objectSpread2["default"])({
    viewBox: "0 0 20 20",
    width: "16px",
    height: "16px"
  }, props), {}, {
    className: "ffont ".concat(props.className ? props.className : ''),
    children: /*#__PURE__*/(0, _jsxRuntime.jsx)("path", {
      d: "M36.2222222,36.2222222 L11.7777778,36.2222222 L11.7777778,11.7777778 L36.2222222,11.7777778 L36.2222222,36.2222222 Z M46,21.5555556 L46,16.6666667 L41.1111111,16.6666667 L41.1111111,11.7777778 C41.1111111,9.06447915 38.9111111,6.88888889 36.2222222,6.88888889 L31.3333333,6.88888889 L31.3333333,2 L26.4444444,2 L26.4444444,6.88888889 L21.5555556,6.88888889 L21.5555556,2 L16.6666667,2 L16.6666667,6.88888889 L11.7777778,6.88888889 C9.06447915,6.88888889 6.88888889,9.06443288 6.88888889,11.7777778 L6.88888889,16.6666667 L2,16.6666667 L2,21.5555556 L6.88888889,21.5555556 L6.88888889,26.4444444 L2,26.4444444 L2,31.3333333 L6.88888889,31.3333333 L6.88888889,36.2222222 C6.88888889,38.922281 9.077719,41.1111111 11.7777778,41.1111111 L16.6666667,41.1111111 L16.6666667,46 L21.5555556,46 L21.5555556,41.1111111 L26.4444444,41.1111111 L26.4444444,46 L31.3333333,46 L31.3333333,41.1111111 L36.2222222,41.1111111 C38.922281,41.1111111 41.1111111,38.922281 41.1111111,36.2222222 L41.1111111,31.3333333 L46,31.3333333 L46,26.4444444 L41.1111111,26.4444444 L41.1111111,21.5555556 L46,21.5555556 Z M26.4444444,26.4444444 L21.5555556,26.4444444 L21.5555556,21.5555556 L26.4444444,21.5555556 L26.4444444,26.4444444 Z M31.3333333,16.6666667 L16.6666667,16.6666667 L16.6666667,31.3333333 L31.3333333,31.3333333 L31.3333333,16.6666667 Z",
      fillRule: "evenodd"
    })
  }));
};
exports.Verilog = Verilog;