@toreda/strong-types
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Better TypeScript code in fewer lines.
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{"version":3,"sources":["../src/arch.ts"],"names":[],"mappings":"AAAA;;;;GAIG;AACH,oBAAY,IAAI;AACf;;;;;;GAMG;AACD,KAAK;AACP;;;;GAIG;GACD,KAAK;AACP;;;;GAIG;GACD,QAAQ;AACV;;;;;GAKG;GACD,KAAK;AACP;;;;GAIG;GACD,OAAO;AAET;;;;;;GAMG;GACD,MAAM;AACR;;;;;;;;GAQG;GACD,SAAS;AACX;;;GAGG;GACD,SAAS;AACX;;;;;IAKI;GACF,OAAO,CAAC","file":"arch.d.ts","sourcesContent":["/**\n * Major processor architectures.\n *\n * @category System Info\n */\nexport type Arch =\n\t/**\n\t * ARC (Argonaut RISC Core) embedded processors. Family of 32-bit and\n\t * 64-bit central processing units (CPUs) originally designed by ARC\n\t * International.\n\t *\n\t * See: https://en.wikipedia.org/wiki/ARC_(processor)\n\t */\n\t| 'arc'\n\t/**\n\t * Intel's x86 architecture family.\n\t *\n\t * See: https://en.wikipedia.org/wiki/X86\n\t */\n\t| 'x86'\n\t/**\n\t * x86-64 (also known as x64, x86_64, AMD64, and Intel 64)\n\t *\n\t *\tSee: https://en.wikipedia.org/wiki/X86-64\n\t */\n\t| 'x86_64'\n\t/**\n\t * Advanced RISC Machines. Reduced instruction set computing (RISC) architectures\n\t * for computer proceessors, configured for various environments.\n\t *\n\t * See: https://en.wikipedia.org/wiki/ARM_architecture\n\t */\n\t| 'arm'\n\t/**\n\t * 64-bit extension of the ARM architecture.\n\t *\n\t * See: https://en.wikipedia.org/wiki/AArch64\n\t */\n\t| 'arm64'\n\n\t/**\n\t * MIPS (Microprocessor without Interlocked Pipelined Stages)[1] is a reduced instruction\n\t * set computer (RISC) instruction set architecture (ISA)[2]: A-1 [3]: 19 developed by MIPS\n\t * Computer Systems, now MIPS Technologies.\n\t *\n\t * See: https://en.wikipedia.org/wiki/MIPS_architecture\n\t */\n\t| 'mips'\n\t/**\n\t * PowerPC (Performance Computing, sometimes abbreviated as PPC). Rreduced instruction\n\t * set computer (RISC) instruction set architecture (ISA) created by the 1991\n\t * Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set,\n\t * has since 2006 been named Power ISA, while the old name lives on as a trademark for\n\t * some implementations of Power Architecture–based processors.\n\t *\n\t * See: https://en.wikipedia.org/wiki/PowerPC\n\t */\n\t| 'powerpc'\n\t/**\n\t * Intel's 64-bit microprocessor that implement the Intel Itanium architecture.\n\t * See: https://en.wikipedia.org/wiki/Itanium\n\t */\n\t| 'itanium'\n\t/**\n\t * SPARC (Scalable Processor Architecture). Reduced instruction set computing\n\t * (RISC) instruction set architecture originally developed by Sun Microsystems\n\t *\n\t * See: https://en.wikipedia.org/wiki/SPARC\n\t **/\n\t| 'sparc';\n"]}